The present invention relates, in general, to electronics, and more particularly, to methods of forming semiconductor devices and structure.
In the past, the semiconductor industry utilized various techniques to form low on-resistance semiconductor devices such as field effect transistors. One particular method utilized a buried layer disposed in a doped region that has a conductivity that is opposite to the conductivity of the substrate. One example of a similar device is disclosed in U.S. Pat. No. 6,168,983. Transistors formed according to the methods disclosed in the above referenced patent often had an on-resistance that changed or drifted after the transistor was manufactured thereby resulting in a higher on-resistance than desired. Additionally, there was not a low conductance path to contact the doped region. Therefore, the resulting on-resistance was greater than desired due to changes in the transistor characteristics required to achieve the desired breakdown voltage.
Accordingly, it is desirable to have a semiconductor device that has an on-resistance that does not substantially drift after the device is manufactured, and that has a low on-resistance.